1. Field of the Invention
This disclosure relates to a nonvolatile memory device, and more particularly, to a power detector for use in a flash memory device.
2. Description of the Related Art
A semiconductor memory device is generally classified into either a volatile memory for which stored information expires by a power failure, or a nonvolatile memory in which the stored information is preserved even with a power failure. The nonvolatile memory may further be classified into an EPROM(Erasable Programmable Read Only Memory), an EEPROM(Electrically Erasable Programmable Read Only Memory) or a flash memory. The flash memory has advantages over the EPROM and the EEPROM, while employing the drive principle of the EPROM when programming data, and employing the drive principle of the EEPROM when erasing the data. In the flash memory the size of the chip is relatively small compared with the EEPROM, thus the flash memory is more usable for high-integration and high capacity, and has an advantage of instantly updating information in a system, etc.
The flash memory requires a relatively high voltage in comparison to the power source used for programming and erasing data. For example, in the programming operation a high voltage of about 10V, or about 5V to 6V, is required, and in the erasing operation a high voltage of about 6V is required. Thus, the flash memory device requires a high voltage generating circuit for generating voltages high in comparison with a power source of about 3V. The high voltage generating circuit for generating high voltage is disclosed in U.S. Pat. No. 5,280,420.
FIG. 1 is a block diagram of an external power apparatus for use in a nonvolatile semiconductor memory device that is provided with a high-voltage generating circuit according to the conventional art. FIG. 2 is a timing diagram for the operation of a power detecting apparatus in an internal power mode according to the conventional art. FIG. 3 is a timing diagram for the operation of a power detecting apparatus in an external power mode according to the conventional art.
The configuration and operation of the power detecting apparatus will be described with reference to FIGS. 1 to 3 according to the conventional art.
Referring to FIG. 1, the power detecting apparatus includes high voltage generators 106a, 106b, 106c, a high voltage level detector 110 and a pulse generator 112. In order to describe the operation of the power detecting apparatus, a command register 102 and a program controller 104 are also shown in FIG. 1.
In the programming operation of the nonvolatile memory device, a program operation in response to command codes causes the command register 102 to generate a program enable signal PGM. The program controller 104 then generates a high voltage enable signal VPP_en, and the high voltage generators 106a, 106b, 106c respond by individually generating voltages VPP1, VPP2, VPP3, respectively, each having a target level. In response to either an internal power mode signal Mint or an external power mode signal Mext, the high voltage level detector 110 outputs a detection signal VPP_OK for the program operation when the voltages VPP1, VPP2, and VPP3 reach their respective target levels. Also, if any one of the voltages VPP1, VPP2, or VPP3 does not reach their respective target level within a predetermined time, t1, the high voltage level detector 110 outputs the detection signal VPP_OK at the end of the predetermined time. Finally, the pulse generator 112 generates a pulse signal HV_OK when the detection signal VPP_OK is enabled.
Referring to FIG. 2, a timing diagram for the case of the internal power mode, when the voltages (1: VPP1, VPP2, VPP3) generated in the high voltage generators reach their respective target levels, the high voltage level detector 110 outputs the detection signal VPP_OK. But when any one of the voltages (2: VPP1, VPP2, VPP3) does not reach their respective target level within a predetermined time, t1, the high voltage level detector 110 also outputs the detection signal VPP_OK, but only after a lapse of the predetermined time.
Referring to FIG. 3, for the case of the external power mode, similar to the case of the internal power mode, when the voltages (3: VPP1, VPP2, VPP3) reach their respective target levels, the high voltage level detector 110 outputs the detection signal VPP_OK. But when any one of the voltages (4: VPP1, VPP2, VPP3) does not reach their respective target level within a predetermined time, t1, the high voltage level detector 110 also outputs the detection signal VPP_OK, but only after a lapse of the predetermined time.
According to the conventional art, as in the case of the internal power mode, a high voltage level detection is also performed in the external power mode. Thus if any one of voltages generated in the high voltage generators does not reach a target level, the high voltage level detector outputs a detection signal for a program operation only after a lapse of a predetermined time. This results in unnecessary time and power loss in the external power mode using an external power source.